1. The Field of the Invention
The present invention relates to methods of forming a conductive structure over a charge conducting region. More particularly, the present invention relates to methods of forming a vertically oriented structure composed of conductive material projecting from a charge conducting region. The method of the present invention is particularly useful for forming a capacitor storage node between two gate stacks situated on a semiconductor substrate.
2. The Relevant Technology
Integrated circuits provide the logic and memory of computers and other intelligent electronic products. These tiny chips have advanced in capability to a level that has made the computers and other intelligent electronic devices in which the integrated circuits operate highly functional. Integrated circuits are also being manufactured economically, allowing the highly functional computers and other intelligent electronic products to be provided to consumers at an affordable cost.
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above. The conventional semiconductor devices which are formed on the semiconductor wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate.
The computer and electronics industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the capabilities of integrated circuits, and to reduce the cost of integrated circuits. One manner of accomplishing this task is to increase the density with which the semiconductor devices can be formed on a given surface area of a single semiconductor wafer. In so doing, the semiconductor devices must be decreased in dimension in a process known as miniaturization. In order to meet market demands and further the miniaturization of integrated circuits, the processes by which the semiconductor devices are formed are in need of improvement. The challenge in miniaturizing integrated circuits is to do so without greatly increasing the cost of the processes by which integrated circuits are manufactured. Accordingly, the new processes must also be relatively simple and cost effective.
One structure which is frequently formed in integrated circuit manufacturing and for which improved methods of formation are needed is the capacitor. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. The storage node and the cell plate are typically patterned out of polysilicon by conventional photolithography and dry etching. The dielectric layer is formed in an intervening process between the formation of the storage node and the cell plate, typically by growth of silicon dioxide through exposure of the polysilicon of the storage node to oxygen at an elevated temperature.
An important consideration in forming capacitors in integrated circuits is surface area. A large surface area of the storage node and cell plate is necessary in order to provide high capacitance and therefore optimal performance of the capacitor. Balanced against this need is the competing requirement that the capacitor also occupy a minimum of space on the semiconductor substrate on which the capacitor is formed. One manner in which the semiconductor industry has approached minimal space capacitor formation is to form the capacitor at a significant distance above the semiconductor substrate. When so doing, one of the storage node and the cell plate are typically wrapped around the other, forming what is known as a stacked capacitor.
The use of container capacitors has effectively increased capacitor surface area, but the formation of container capacitors presents new problems. One such problem involves making electrical contact between the container capacitor and an underlying source/drain region through a relatively narrow area between two gate stacks. One example of the occurrence of such a problem is in the formation of a metal oxide silicon dynamic random access memory (MOS DRAM) cell, where a container capacitor is formed above two word line gate stacks.
Shown in FIG. 1 is a typical arrangement of the basic structure used in the formation of a MOS DRAM memory cell. Shown therein is semiconductor structure 10 formed with a silicon substrate 12 on which are located a plurality of source/drain regions 12a. A pair of gate stacks, generally seen at reference numeral 14, serve as word lines and provide control signals to the memory cell. Gate stacks 14 are situated on silicon substrate 12, one gate stack 14 at either side of the center source/drain region 12a. Each gate stack 14 is provided at the top and sides thereof with a protective silicon nitride spacer 14a. Miniaturization demands require that gate stacks 14 be closely spaced. Thus a relatively narrow open space 16 is defined between gate stacks 14 and over the center source/drain region 12a. 
Typically in the formation of a container capacitor, a storage node is formed above source/drain region 12a projecting upwards therefrom for a distance above gate stacks 14. To form the storage node, a layer of insulating material such as a borophosphosilicate glass (BPSG) layer is formed over gate stacks 14 and source/drain region 12a therebetween. Open space 16, seen in FIG. 1, is then etched into the BPSG layer in which to form the container capacitor. Open space 16 extends from the top most surface of the BPSG layer down to source/drain region 12a in between gate stacks 14. Once formed, the storage node will be situated upon source/drain region 12a in between gate stacks 14.
Problems arise in removing BPSG material to form open space 16 which is typically narrower than about 0.2 microns, a distance not readily achievable with conventional photolithography resolution. Therefore, in order to form open space 16, the BPSG layer must be patterned such that the subsequent etch of the BPSG layer creates an opening above open space 16 that is wider than open space 16. If the etch of the BPSG layer is selective to silicon nitride cap 14a, the etch form open space 16 such that it is self-aligned between gate stacks 14. Self-alignment ensures that, if the etched opening above open space 16 is slightly misplaced in initial alignment between gate stacks 14 and the source/drain region 12a therebetween, open space 16 will still be situated between gate stack 14 so as to expose source/drain region 12a therebetween.
Conventional self-alignment processes have several drawbacks which are advantageous to avoid. For instance, a dry etching process such as reactive ion etching (RIE) or milling RIE (MRIE) is typically used to form the opening to open space 16, and must also clear BPSG material from open space 16. In so doing, it is difficult to terminate the dry etching without etching into the silicon of source/drain region 12a between gate stacks 14. It is also difficult to maintain a uniformity of the dry etching process across the entirety of semiconductor structure 10 when etching into multiple open spaces 16 situated across semiconductor structure 10, such that all open spaces 16 are fully cleared of BPSG material without etching into respective source/drain regions 12a. 
Thus, the etching must clear BPSG material to form open space 16 without substantially etching the silicon of silicon substrate 12 where source/drain region 12a is situated. As discussed, such a selective etch is difficult to conduct, and the consequences of over-etching are severe, as etching into source/drain region 12a causes shorting and results in a defective condition of the entire integrated circuit.
Further problems arise in forming a container capacitor once open space 16 has been cleared of BPSG. One such problem occurs when depositing a capacitor storage node in the completed opening. When so doing, the material of the capacitor storage node tends to coalesce into the center of open space 16 so as to fill up much of open space 16, and thus making open space 16 largely inaccessible for the formation of the container capacitor therein.
One prior art process directed to remedying these problems utilizes a landing pad formed in open space 16. One common manner of utilizing a landing pad in container capacitor formation is shown in FIG. 2 and comprises forming the landing pad from a polysilicon plug 24 that fills open space 16. Polysilicon plug 24 eliminates the need for selectively etching BPSG material to form open space 16. The formation of polysilicon plug 24 is problematic in that it consumes fabrication time to deposit, and due to the thickness thereof. Also, polysilicon plug 24 fills the entirety of open space 16, thus preventing the formation of the container capacitor therein and consequently reducing the density within which the container capacitor cell can be formed.
Forming a landing pad only in a bottom portion of open space 16 has also been attempted, but has proven difficult, as the landing pad is time consuming to form and still must be sufficiently thick to compensate for non-uniformity in etching across semiconductor wafer 10. Also, the landing pad, although only in a bottom portion of open space 16, still consumes much of open space 16.
Consequently, an improved method is needed that overcomes the above-discussed problems inherent to forming a conductive structure in a narrow space above a source/drain region. Such a method would preferably form a landing pad in a manner that also overcomes the above-discussed problems of the prior art landing pads, including fabrication time, and the inherent low density in which a container capacitor can be formed. In addition, such a method is needed that can be conducted in a simple and cost effective manner.
The present invention resolves the above-described problems by providing an improved method of using a landing pad to form a vertically oriented structure in an open space above a charge conducting region.
In one embodiment of the method of the present invention where the vertically oriented structure comprises a storage node of a container capacitor, a charge conducting region in the form of a source/drain region is initially provided on a semiconductor substrate. Also provided on the semiconductor substrate is a pair of gate stacks that are located one to either side of the source/drain region. The gate stacks are closely spaced such that an open space is formed between the gate stacks and over the source/drain region. The open space preferably has a width of about 0.1 microns.
A layer of a conductive material is subsequently deposited in the open space and upon the source/drain region. A landing pad is patterned and etched from the layer of conductive material so as to line the sides and bottom of the open space, but not so as to substantially fill the open space. The landing pad also extends over at least a portion of the top of each gate stack.
Once the landing pad is formed, a layer of insulating material, such as a BPSG layer, is subsequently formed over the landing pad. The BPSG layer is formed with a height corresponding to the intended height of the capacitor storage node to be formed. A recess is then anisotropically etched wider than the open space through the BPSG layer to terminate at and expose a portion of the landing pad located on the tops of the gate stacks. A volume of BPSG is left remaining on the landing pad within the open space between the pair of gate stacks.
Next, a polysilicon layer or other layer of conductive material is deposited so as to line and partially fill the recess. The polysilicon layer preferably makes an annular region of contact with the exposed surface on the landing pad. A segment of the polysilicon layer also covers the volume of BPSG on the landing pad.
After depositing the polysilicon layer, an anisotropic etching process is conducted to remove the segment of the polysilicon layer covering the volume of BPSG on the landing pad. The isotropic etching process preferably may be a dry etch. The volume of BPSG on the landing pad is exposed as a result of the anisotropic etching process. The landing pad and polysilicon layer at this point form a continuous conductive layer around the recess and the open space and containing the volume of BPSG on the landing pad.
In an optional further procedure, the volume of BPSG on the landing pad is removed so as to expose the portion of the landing pad that extends into the recess between the pair of gate stacks such that the recess extends down below the tops of the gate stacks. Removing the volume of BPSG on the landing pad increases the surface area of the resulting capacitor that can be formed thereby, and consequently increases the capacitor charge retention and refresh rates thereof. A further optional procedure comprises roughening the surface of the landing pad and polysilicon layer to increase the surface area thereof. In one embodiment, roughening of the surface of the landing pad and the polysilicon layer is achieved through formation of a layer of hemispherical grained (HSG) polysilicon or cylindrical grained polysilicon (CGP) on exposed surfaces of the landing pad and the polysilicon layer.
The landing pad and the polysilicon layer line the open space and the recess, which together in one embodiment form a capacitor storage node. A capacitor incorporating the capacitor storage node is completed by forming a dielectric layer in the recess and the open space, after which a cell plate is formed thereover. The cell plate is preferably formed of polysilicon.
In an alternate embodiment, the BPSG layer is partially reduced in height concurrent with a substantially total removal of the volume of BPSG on the landing pad. Reducing the height of the BPSG layer exposes the entire circumference of a top portion of the polysilicon layer and allows a capacitor dielectric and cell plate to be formed on both sides thereof, further increasing capacitor surface area.
The method of the present invention as described above forms a container capacitor in a simplified manner and without the need for a dry etching process that is highly selective to the silicon of the source/drain region. Also, the capacitor surface area increases in that the resulting capacitor extends into the open space. Densification and miniaturization are facilitated by greater capacitor surface area being formed in a smaller foot print on the semiconductor wafer. The landing pad is also thinner than prior art landing pads, such as polysilicon plug 24 discussed above, thus saving process time in the deposition thereof and thereby increasing integrated circuit manufacturing throughput.
These and other features, and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.